Wire sizing as a convex optimization problem: exploring the area-delay tradeoff

It is rapidly becoming obvious that with the current trends in technology, interconnect delays are becoming an increasingly dominant factor in determining circuit speed. Until recently, interconnect resistance was often insigni cant, while its capacitance was not, and hence optimal interconnect design frequently involved ensuring that all wire sizes were minimal. However, with advancement in technology, reduction in circuit geometries, increases in circuit speeds, and the advent of MCM's, the wire sizing problem for interconnect optimization has become signi cant.